Experimental Evaluation of a Hartley Oscillator Incorporating a Commercial SDC Memristor.
DOI:
https://doi.org/10.66131/JDSC13202623-35Keywords:
Memristor, Hartley, Oscillator, Frequency, AmplitudeAbstract
This paper experimentally investigates integrating a commercial Self-Directed Channel (SDC) memristor into a Hartley oscillator. While most existing literature relies on theoretical models or emulators, this work utilizes a physical W-type (Tungsten) memristor to analyze its direct impact on the oscillator’s periodic steady-state response. The experimental setup, implemented with a TL081CD operational amplifier and an Analog Discovery Studio platform, demonstrates that the memristor acts as a dynamic feedback element.
Comparative results show that including the memristive device increases the peak-to-peak amplitude by 34% (from 2.724 V to 3.65 V) and shifts the frequency down from 14.530 kHz to 14.213 kHz. Furthermore, the memristor-based oscillator showed an additional startup interval of about 2 s, with an estimated relative variation of ±27% across repeated experiments. This behavior suggests a modified oscillator transient response, potentially linked to the SDC device’s history-dependent electrical characteristics. The results indicate that the memristor-augmented Hartley oscillator maintains a stable sinusoidal waveform, suggesting that the device’s state-dependent resistance can effectively modulate the system’s gain and resonance conditions in analog circuit architectures.
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Copyright (c) 2026 Luis Manuel Lopez Jimenez, Alejandro Diaz Sanchez, Esteban Tlelo Cuautle
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
